CMOS imagers are known in the art. Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524, and 6,333,205, each assigned to Micron Technology, Inc. The disclosures of the forgoing patents are hereby incorporated by reference in their entirety.
A typical pixel of a CMOS image sensor cell, in a 4T (four transistor) layout, includes a photodiode as a photoconversion device, a transfer gate for transferring photoelectric charges generated in the charge accumulating region of the photodiode to a floating diffusion region (sensing node). The floating diffusion region is typically connected to a gate of a source follower transistor. The source follower transistor provides an output signal to a row select access transistor having gate for selectively gating the output signal to a column line of a pixel cell. A reset transistor resets the floating diffusion region using a supply voltage applied at a source/drain region to a specified charge level before each charge transfer from the charge accumulating region of the photodiode. The pixel is typically isolated from other like cells of an imager array by shallow trench isolation regions. A 3T (three transistor) pixel cell works similarly, but does away with the transfer transistor, instead directly transferring charge from the photodiode to the source follower transistor.
Pinned photodiodes are utilized in image sensor technology in both CCD and CMOS imagers. A pinned photodiode is termed “pinned” because the potential in the photodiode is held to a constant value when the photodiode is fully depleted. A pinned photodiode typically includes an n-type conductivity charge accumulating region bound on the top and bottom by p-type conductivity layers; the top being an implanted layer and the bottom one being the substrate upon which the image sensor pixel is formed. It is also possible to utilize an oppositely doped scheme where the charge accumulating region is p-type. A pinned photodiode reduces the impact from surface states (trapped sites; dangling bonds) in silicon. Besides lower pixel noise, the pinned photodiode offers reduced dark current, due to quenching of surface-interface traps and improved blue response, since it is easier to collect “blue electrons” generated near the silicon-silicon-dioxide interface with the pinned photodiode.
In p+/n−/p− pinned photodiodes, the top surface is typically highly doped with acceptors by implantation. Such implants tend to create a tail distribution and lateral spread, depending on the species of implant (typically boron, BF2) energy, and dosage. This presents two issues: compensation of n− diode region, and therefore, reduced fill factor; and deeper p+/n junction, which leads to complex optimization issues for the photodiode and transfer gate region.
In all integrated circuit technology, of which image sensor devices are a part, there is a constant desire to scale down the sizes of devices and at the same time increase their density. As image sensors having pinned photodiodes are scaled down, the photodiode necessarily gets a smaller and it becomes harder to create the pinning effect in the photodiode as the charge accumulating n-type region of the photodiode nears the surface of the substrate. The n-region of the photodiodes are necessarily kept away from the substrate surface, which has trap sites that could interfere with the photodiode operation. To compensate for the smaller photodiode area the n-region is pushed further into the substrate, gaining size in depth where it was lost in width so that fill factor reduction is mitigated. However, such changes in photodiode shape can lead to cross-talk between pixels as the photodiodes expand below the isolation structures (e.g., shallow trench isolation—STI).